1. Field of the Invention
This invention relates generally to the packaging of semiconductor devices for use in computers, and more particularly to packaging of full wafers of silicon having integrated circuit devices formed thereon.
2. Description of the Prior Art
In the semiconductor art, large numbers of integrated circuit devices defining complex integrated circuits are formed on semiconductor materials, such as silicon wafers, by techniques which are well known in the art; and, as technology advances, larger wafers can be used in the manufacturing process with attendant cost savings. Typically the wafers are cut or otherwise diced to form a large number of individual integrated circuit chips. These chips are then mounted individually, or in groups, on suitable substrates, such as metalized ceramic material. Several such substrates having chips mounted are then typically mounted on cards or boards to form the electronic circuitry of a computer or other product.
In order to improve the efficiency and effectiveness of packaging integrated circuits, there have been prior art proposals to package an entire wafer as a whole, rather than dicing the wafer into individual chips thereby achieving increased efficiency in packaging density, as well as eliminating the need for the dicing and associated processes. One such proposal is shown and described in U.S. Pat. No. 3,999,105, assigned to the assignee of this invention. In the 3,999,105 patent, a packaging technique is described wherein a full wafer is mounted on a wafer carrier. Pins are provided around the periphery of the carrier to bring power to the wafer, and carriers with wafers thereon are mounted within a housing. The carrier and thus the wafers are electrically connected by pin interconnections, and the housing is sealed and filled with a liquid coolant, the cooling being accomplished by nucleate boiling.
While this type of packaging has some advantages, it has several drawbacks which have prevented it from achieving wide acceptance. One of the principal drawbacks with this full wafer packaging technique is the problem associated with providing adequate electrical power in a timely manner to efficiently and reliably perform the electrical operations. This is in large measure due to the fact that the electrical power has been supplied from around the periphery of the wafer, and by supplying the power at the periphery, a significant voltage drop occurred from the outer edge to devices in the center, since by virtue of its structure the metal lines carrying the power are of limited size. Also the distance and voltage requirements result in quite slow operation of device drivers, which can have very short signal rise times in modern CMOS technology.
Another drawback to this particular technique is the liquid cooling technique, which is not completely reliable and rather inefficient.
Still a further drawback to full wafer mounting technology is the very great sensitivity of the structure to thermal mismatch of the wafer and the supporting substrate, which if present even in a relatively small degree can result in cracking with attendant device and circuit malfunction.